8
LTC1422
1422fb
APPLICATIONS INFORMATION
U
U
U
V
OUT
TIMER
RESET
V2
V2
V2
V1
V1
1.232V
1.232V
1
2
3
4
1422 F04
Figure 4. Supply Monitor Waveforms
When the voltage at the FB pin rises above its reset
threshold (1.232V), the comparator COMP 2 output goes
high, and a timing cycle starts (Figure 4, time points 1 and
4). After a complete timing cycle, RESET is pulled high.
The 12礎 pull-up current source to V
CC
on RESET has a
series diode so the pin can be pulled above V
CC
by an
external pull-up resistor without forcing current back into
supply.
When the supply voltage at the FB pin drops below its reset
threshold, the comparator Comp 2 output goes low. After
passing through a glitch filter, RESET is pulled low (time
point 2). If the FB pin rises above the reset threshold for
less than a timing cycle, the RESET output will remain low
(time point 3).
Glitch Filter
The LTC1422 has a glitch filter to prevent RESET from
generating a system reset when there are transients on the
FB pin. The filter is 20祍 for large transients (greater than
150mV) and up to 80祍 for small transients. The relation-
ship between glitch filter time and the transient voltage is
shown in Typical Performance curve: Glitch Filter Time vs
Feedback Transient.
Soft Reset
In some cases a system reset is desired without a power
down. The ON pin can signal the RESET pin to go low
without turning off the external N-channel (a soft reset).
This is accomplished by holding the ON pin low for only
15祍 or less (Figure 5, time point 1). At about 30祍 from
the falling edge of the ON pin (time point 2) the RESET pin
goes low and stays low for one timing cycle.
Figure 5. Soft Reset Waveforms
ESET
V
OUT
GATE
1422 F
IMER
ON
30祍
1
2
30祍 (typ)
3
4
6
5
15祍
20 s
If the ON pin is held low for longer than 30祍 (typ), the gate
will turn off and the RESET pin will eventually go low (time
points 4, 5 and 6).
Timer
The system timing for the LTC1422 is generated by the
circuitry shown in Figure 6. The timer is used to set the
turn-on delay after the ON pin goes high and the delay
before the RESET pin goes high after the output supply
voltage is good as sensed by the FB pin.
+
SENSE
TIMER
2礎
R4
R3
R2
7
V
CC
V
OUT
V
CC
8
GATE
LTC1422
6
2
ON
1422 F06
SUPPLY
MONITOR
1
5
C2
3
4
RESET
C1
C
LOAD
Q2
R1
LOGIC
1.232V
+
COMP 4
Q1
Figure 6. System Timing Block Diagram
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